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CY7C1460KV33 Datasheet(PDF) 12 Page - Cypress Semiconductor

Part No. CY7C1460KV33
Description  36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1460KV33 Datasheet(HTML) 12 Page - Cypress Semiconductor

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Document Number: 001-66680 Rev. *L
Page 12 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1460KV33/CY7C1460KVE33 follows. [8, 9, 10, 11]
Function (CY7C1460KV33/CY7C1460KVE33)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – no bytes written
L
H
H
H
H
Write byte a – (DQa and DQPa)L
H
H
H
L
Write byte b – (DQb and DQPb)L
H
H
L
H
Write bytes b, a
L
H
H
L
L
Write byte c – (DQc and DQPc)L
H
L
H
H
Write bytes c, a
L
H
L
H
L
Write bytes c, b
L
H
LL
L
H
Write bytes c, b, a
L
H
L
L
L
Write byte d – (DQd and DQPd)L
L
H
H
H
Write bytes d, a
L
L
H
H
L
Write bytes d, b
L
L
H
L
H
Write bytes d, b, a
L
L
H
L
L
Write bytes d, c
L
L
L
H
H
Write bytes d, c, a
L
L
L
H
L
Write bytes d, c, b
L
L
L
L
H
Write all bytes
LLL
LL
Partial Write Cycle Description
The Partial Write Cycle Description for CY7C1462KVE33 follows. [9, 11]
Function (CY7C1462KVE33)
WE
BWb
BWa
Read
H
x
x
Write – no bytes written
L
H
H
Write byte a – (DQa and DQPa)L
H
L
Write byte b – (DQb and DQPb)L
L
H
Write both bytes
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BWX. See Write Cycle Description table for details.
10. When a write cycle is detected, all I/Os are tristated, even during byte writes.
11. Table only lists partial byte write combinations. Any combination of BW[a:d] is valid. Appropriate write is done based on which byte write is active.


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