CY7C1441KV33

CY7C1443KV33

CY7C1441KVE33

Document Number: 001-66677 Rev. *I

Page 7 of 32

Pin Definitions

Name

I/O

Description

Input-Synchronous Address Inputs Used to Select One of the Address Locations. Sampled at the

the SRAM. Sampled on the rising edge of CLK.

GW

Input-Synchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of

CLK, a global write is conducted (ALL bytes are written, regardless of the values on

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in

Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in

a new external address is loaded.

Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in

is loaded.

OE

Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O

pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins

are tristated, and act as input data pins. OE is masked during the first clock of a read

cycle when emerging from a deselected state.

ADV

Input-Synchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-Synchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active

LOW. When asserted LOW, addresses presented to the device are captured in the

HIGH.

ADSC

Input-Synchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active

LOW. When asserted LOW, addresses presented to the device are captured in the

are both asserted, only ADSP is recognized.

BWE

Input-Synchronous Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal

must be asserted LOW to conduct a byte write.

ZZ

Input-Asynchronous ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a

non-time-critical “sleep” condition with data integrity preserved. For normal operation,

this pin must be LOW or left floating. ZZ pin has an internal pull down.

I/O-Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave

are automatically tristated during the data portion of a write sequence, during the first

clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.