ADN2819ACP-CML-RL datasheet(4/24 Pages) AD

Part #	ADN2819ACP-CML-RL

Description	Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

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ADN2819

Rev. B | Page 4 of 24

Parameter

Conditions

Min

Typ

Max

Unit

Hysteresis (Electrical) (continued)

OC-3, PRBS 27

RTHRESH = 2 kΩ

5.4

6.6

7.7

dB

RTHRESH = 20 kΩ

4.6

6.4

8.2

dB

RTHRESH = 90 kΩ

3.9

6.8

9.7

dB

LOSS OF LOCK DETECTOR (LOL)

Loss of Lock Response Time

From fVCO error > 1000 ppm

60

mV

POWER SUPPLY VOLTAGE

3.0

3.3

3.6

V

POWER SUPPLY CURRENT

150

164

215

mA

PHASE-LOCKED LOOP CHARACTERISTICS

PIN–NIN = 10 mV p-p

Jitter Transfer BW

OC-48

590

880

kHz

GbE

310

480

kHz

OC-12

140

200

kHz

OC-3

48

85

kHz

Jitter Peaking

OC-48

0.025

dB

OC-12

0.004

dB

OC-3

0.002

dB

Jitter Generation

OC-48, 12 kHz–20 MHz

0.003

UI rms

0.05

0.09

UI p-p

OC-12, 12 kHz–5 MHz

0.002

UI rms

0.02

0.04

UI p-p

OC-3, 12 kHz–1.3 MHz

0.002

UI rms

0.02

0.04

UI p-p

Jitter Tolerance

OC-48 (See Figure 14)

600 Hz3

92

UI p-p

6 kHz3

20

UI p-p

100 kHz

5.5

UI p-p

1 MHz3

1.0

UI p-p

GbE (OC-24) (See Figure 14)

300 Hz3

16

UI p-p

3 kHz3

16

UI p-p

50 kHz

7.7

UI p-p

500 kHz3

2.2

UI p-p

OC-12 (See Figure 14)

30 Hz3

100

UI p-p

300 Hz

44

UI p-p

25 kHz

5.8

UI p-p

250 kHz3

1.0

UI p-p

OC-3 (See Figure 14)

30 Hz3

50

UI p-p

300 Hz3

23.5

UI p-p

6500 Hz

6.0

UI p-p

65 kHz3

1.0

UI p-p

CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)

Single-Ended Output Swing

VSE (See Figure 7)

300

455

600

mV

Differential Output Swing

VDIFF (See Figure 7)

600

910

1200

mV

Output High Voltage

VOH

VCC

V

Output Low Voltage

VOL, referred to VCC

–0.60

–0.30

V

Rise Time

20%–80%

150

ps

Fall Time

80%–20%

150

ps

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