CY7C1440KV33

CY7C1442KV33

CY7C1440KVE33

Document Number: 001-66676 Rev. *G

Page 7 of 33

Pin Definitions

Name

I/O

Description

Input-synchronous

Address inputs used to select one of the address locations. Sampled at the rising

sampled active. A1: A0 are fed to the two-bit counter.

the SRAM. Sampled on the rising edge of CLK.

GW

Input-synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of

and BWE).

BWE

Input-synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal

must be asserted LOW to conduct a byte write.

CLK

Input-clock

Clock input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in

Input-synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in

a new external address is loaded.

Input-synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in

is loaded.

OE

Input-asynchronous Output enable, asynchronous input, active LOW. Controls the direction of the I/O

pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins

are tri-stated, and act as input data pins. OE is masked during the first clock of a read

cycle when emerging from a deselected state.

ADV

Input-synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When

asserted, it automatically increments the address in a burst cycle.

ADSP

Input-synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are

HIGH.

ADSC

Input-synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are

both asserted, only ADSP is recognized.

ZZ

Input-asynchronous ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a

non-time-critical “sleep” condition with data integrity preserved. For normal operation,

this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

I/O-synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave

Power supply

Power supply inputs to the core of the device.

Note

1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.