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CY7C1440KV33 Datasheet(PDF) 23 Page - Cypress Semiconductor

Part # CY7C1440KV33
Description  36-Mbit (1M36/2M18) Pipelined Sync SRAM (With ECC)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1440KV33 Datasheet(HTML) 23 Page - Cypress Semiconductor

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CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Document Number: 001-66676 Rev. *G
Page 23 of 33
Switching Characteristics
Over the Operating Range
Parameter [20, 21]
Description
–250
–167
Unit
Min
Max
Min
Max
tPOWER
VDD(Typical) to the first access[22]
1
1
ms
Clock
tCYC
Clock cycle time
4.0
6
ns
tCH
Clock HIGH
1.5
2.4
ns
tCL
Clock LOW
1.5
2.4
ns
Output Times
tCO
Data output valid after CLK rise
2.5
3.4
ns
tDOH
Data output hold after CLK rise
1.0
1.5
ns
tCLZ
Clock to low Z[23, 24, 25]
1.0
1.5
ns
tCHZ
Clock to high Z[23, 24, 25]
2.6
3.4
ns
tOEV
OE LOW to output valid
2.6
3.4
ns
tOELZ
OE LOW to output low Z[23, 24, 25]
0
0
ns
tOEHZ
OE HIGH to output high Z[23, 24, 25]
2.6
3.4
ns
Set-up Times
tAS
Address set-up before CLK rise
1.2
1.5
ns
tADS
ADSC, ADSP set-up before CLK rise
1.2
1.5
ns
tADVS
ADV set-up before CLK rise
1.2
1.5
ns
tWES
GW, BWE, BWX set-up before CLK rise
1.2
1.5
ns
tDS
Data input set-up before CLK rise
1.2
1.5
ns
tCES
Chip enable set-up before CLK rise
1.2
1.5
ns
Hold Times
tAH
Address hold after CLK rise
0.3
0.5
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
0.5
ns
tADVH
ADV hold after CLK rise
0.3
0.5
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
0.5
ns
tDH
Data input hold after CLK rise
0.3
0.5
ns
tCEH
Chip enable hold after CLK rise
0.3
0.5
ns
Notes
20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 3 on page 22. Transition is measured ± 200 mV from steady-state voltage.
24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.


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