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CY7C1440KV33 Datasheet(PDF) 12 Page - Cypress Semiconductor

Part # CY7C1440KV33
Description  36-Mbit (1M36/2M18) Pipelined Sync SRAM (With ECC)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1440KV33 Datasheet(HTML) 12 Page - Cypress Semiconductor

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CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Document Number: 001-66676 Rev. *G
Page 12 of 33
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1440KV33/CY7C1440KVE33 is as follows. [8, 9, 10]
Function (CY7C1440KV33/CY7C1440KVE33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
XX
XX
Read
H
L
HH
HH
Write byte A – (DQA and DQPA)H
L
H
H
H
L
Write byte B – (DQB and DQPB)H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
LLL
LL
Write all bytes
L
X
X
X
X
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1442KV33 is as follows. [8, 9, 10]
Function (CY7C1442KV33)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)H
L
H
L
Write byte B – (DQB and DQPB)H
L
L
H
Write bytes B, A
H
L
L
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Notes
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
at the same time for any given write.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.


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