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CY7C1440KV33 Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1440KV33
Description  36-Mbit (1M36/2M18) Pipelined Sync SRAM (With ECC)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1440KV33 Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Document Number: 001-66676 Rev. *G
Page 11 of 33
Truth Table
The truth table for CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 is as follows [2, 3, 4, 5, 6, 7].
Operation
Add. Used CE1 CE2 CE3 ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H
Tri-state
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H
Tri-state
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H
Tri-state
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H
Tri-state
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H
Tri-state
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tri-state
WRITE cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tri-state
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
READ cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tri-state
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
READ cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tri-state
WRITE cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
WRITE cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tri-state
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
READ cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tri-state
WRITE cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).


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