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CY7C1440KV33 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1440KV33
Description  36-Mbit (1M36/2M18) Pipelined Sync SRAM (With ECC)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1440KV33 Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
36-Mbit (1M × 36/2M × 18)
Pipelined Sync SRAM (With ECC)
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-66676 Rev. *G
Revised July 5, 2016
36-Mbit (1M × 36/2M × 18) Pipelined Sync SRAM (With ECC)
Features
Supports bus operation up to 250 MHz
Available speed grades are 250 MHz and 167 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply
2.5 V or 3.3 V I/O power supply
Fast clock-to-output time
2.5 ns (for 250 MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1440KV33, CY7C1442KV33 and CY7C1440KVE33 are
available in Pb-free 100-pin TQFP, and Pb-free and non Pb-free
165-ball FBGA packages.
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
On-Chip error correction code (ECC) to reduce soft error rate
(SER)
Functional Description
The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 SRAM
integrate 1M × 36/2M × 18/1M × 36 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The
CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
250 MHz
167 MHz
Unit
Maximum access time
2.5
3.4
ns
Maximum operating current
× 18
220
Not Offered mA
× 36
240
190


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