Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1440KV33 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1440KV33
Description  36-Mbit (1M36/2M18) Pipelined Sync SRAM (With ECC)
Download  33 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1440KV33 Datasheet(HTML) 7 Page - Cypress Semiconductor

Back Button CY7C1440KV33 Datasheet HTML 3Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 4Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 5Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 6Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 7Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 8Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 9Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 10Page - Cypress Semiconductor CY7C1440KV33 Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 33 page
background image
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Document Number: 001-66676 Rev. *G
Page 7 of 33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-synchronous
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[1]are
sampled active. A1: A0 are fed to the two-bit counter.
BWA, BWB, BWC, BWD Input-synchronous Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
Input-synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (all bytes are written, regardless of the values on BWX
and BWE).
BWE
Input-synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
Input-synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ
package version. Not connected for BGA. Where referenced, CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address
is loaded.
OE
Input-asynchronous Output enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are tri-stated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ZZ
Input-asynchronous ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPX
I/O-synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power supply
Power supply inputs to the core of the device.
Note
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.


Similar Part No. - CY7C1440KV33

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1440KV25 CYPRESS-CY7C1440KV25 Datasheet
2Mb / 30P
   36-Mbit (1M 횞 36) Pipelined Sync SRAM
More results

Similar Description - CY7C1440KV33

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1444KV33 CYPRESS-CY7C1444KV33 Datasheet
1Mb / 22P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined DCD Sync SRAM
CY7C1460KV25 CYPRESS-CY7C1460KV25 Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV33 CYPRESS-CY7C1460KV33 Datasheet
1,010Kb / 31P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1440KV25 CYPRESS-CY7C1440KV25 Datasheet
2Mb / 30P
   36-Mbit (1M 횞 36) Pipelined Sync SRAM
CY7C1441KV33 CYPRESS-CY7C1441KV33 Datasheet
1Mb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM (With ECC)
CY7C1460SV25 CYPRESS-CY7C1460SV25 Datasheet
429Kb / 31P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1386KV33 CYPRESS-CY7C1386KV33 Datasheet
390Kb / 23P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined DCD Sync SRAM
CY7C1370KV33 CYPRESS-CY7C1370KV33 Datasheet
999Kb / 32P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1380KV33 CYPRESS-CY7C1380KV33 Datasheet
3Mb / 33P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM
CY7C1381KV33 CYPRESS-CY7C1381KV33 Datasheet
1Mb / 34P
   18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM (With ECC)
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com