CY7C1380KV33-167AXC datasheet(9/33 Pages) CYPRESS

Part #	CY7C1380KV33-167AXC

Description	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

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9 / 33 page

CY7C1380KV33

CY7C1382KV33

Document Number: 001-97878 Rev. *E

Page 9 of 33

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation sleep mode. Two clock cycles

are required to enter into or exit from this sleep mode. While in

this mode, data integrity is guaranteed. Accesses pending when

entering the sleep mode are not considered valid nor is the

completion of the operation guaranteed. The device must be

deselected prior to entering the sleep mode. CE1, CE2, CE3,

ADSP, and ADSC must remain inactive for the duration of tZZREC

after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD– 0.2 V

–

65

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2 V

–

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2 V

2tCYC

–ns

tZZI

ZZ Active to sleep current

This parameter is sampled

–

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current This parameter is sampled

0

–

ns

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CY7C1380KV33-167AXC Datasheet(PDF) 9 Page - Cypress Semiconductor

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