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CY7C1385D Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1385D
Description  18-Mbit (512 K 횞 32) Flow-Through SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1385D Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C1385D
18-Mbit (512 K × 32) Flow-Through SRAM
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-74016 Rev. *C
Revised December 29, 2015
18-Mbit (512 K × 32) Flow-Through SRAM
Features
Supports 133 MHz bus operations
512 K × 32 common I/O
3.3 V core power supply (VDD)
2.5 V or 3.3 V I/O supply (VDDQ)
Fast clock-to-output time
6.5 ns (133 MHz version)
Provides high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1385D is available in JEDEC-standard Pb-free 100-pin
TQFP package
ZZ sleep mode option
Functional Description
The CY7C1385D is a 3.3 V, 512 K × 32 synchronous flow through
SRAMs, designed to interface with high speed microprocessors
with minimum glue logic. Maximum access delay from clock rise
is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWx, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1385D allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an interleaved
burst sequence, while a LOW selects a linear burst sequence.
Burst accesses can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC)
inputs. Address advancement is controlled by the address
advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1385D operates from a +3.3 V core power supply while all
outputs operate with a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
For a complete list of related resources, click here.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
210
mA
Maximum CMOS Standby Current
70
mA


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