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CY7C1381KV33 Datasheet(PDF) 26 Page - Cypress Semiconductor

Part No. CY7C1381KV33
Description  18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
Download  34 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1381KV33 Datasheet(HTML) 26 Page - Cypress Semiconductor

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CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *F
Page 26 of 34
Figure 6. Write Cycle Timing [23, 24]
.
Timing Diagrams (continued)
tCYC
t
CL
CLK
tADH
tADS
ADDRESS
t
CH
tAH
tAS
A1
tCEH
tCES
High-Z
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
t
OEHZ
tADVH
tADVS
tWEH
tWES
t
DH
t
DS
t
WEH
t
WES
Byte write signals are ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE
UNDEFINED
ADSP
ADSC
BWE,
BW
X
GW
CE
ADV
OE
Data in (D)
Data Out (Q)
Notes
23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.


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