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CY7C1381KV33 Datasheet(PDF) 24 Page - Cypress Semiconductor

Part No. CY7C1381KV33
Description  18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
Download  34 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1381KV33 Datasheet(HTML) 24 Page - Cypress Semiconductor

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CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *F
Page 24 of 34
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
133 MHz
100 MHz
Unit
Min
Max
Min
Max
tPOWER
VDD(typical) to the first access [18]
1
–1–
ms
Clock
tCYC
Clock cycle time
7.5
–10–
ns
tCH
Clock HIGH
2.1
–2.5
ns
tCL
Clock LOW
2.1
–2.5
ns
Output Times
tCDV
Data output valid after CLK rise
6.5
8.5
ns
tDOH
Data output hold after CLK rise
2.0
–2.0
ns
tCLZ
Clock to low Z [19, 20, 21]
2.0
2.0
ns
tCHZ
Clock to high Z [19, 20, 21]
0
4.0
0
5.0
ns
tOEV
OE LOW to output valid
3.2
3.8
ns
tOELZ
OE LOW to output low Z [19, 20, 21]
0
0
ns
tOEHZ
OE HIGH to output high Z [19, 20, 21]
4.0
5.0
ns
Setup Times
tAS
Address setup before CLK rise
1.5
–1.5
ns
tADS
ADSP, ADSC setup before CLK rise
1.5
–1.5
ns
tADVS
ADV setup before CLK rise
1.5
–1.5
ns
tWES
GW, BWE, BW[A:D] setup before CLK rise
1.5
–1.5
ns
tDS
Data input setup before CLK rise
1.5
–1.5
ns
tCES
Chip enable setup
1.5
–1.5
ns
Hold Times
tAH
Address hold after CLK rise
0.5
–0.5
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–0.5
ns
tWEH
GW, BWE, BW[A:D] hold after CLK rise
0.5
–0.5
ns
tADVH
ADV hold after CLK rise
0.5
–0.5
ns
tDH
Data input hold after CLK rise
0.5
–0.5
ns
tCEH
Chip enable hold after CLK rise
0.5
–0.5
ns
Notes
16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be
initiated.
19. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system condition.
21. This parameter is sampled and not 100% tested.


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