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CY7C1381KV33 Datasheet(PDF) 21 Page - Cypress Semiconductor

Part No. CY7C1381KV33
Description  18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
Download  34 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1381KV33 Datasheet(HTML) 21 Page - Cypress Semiconductor

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CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *F
Page 21 of 34
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0 °C to +70 °C
3.3 V
– 5% /
+ 10%
2.5 V – 5% to
VDD
Industrial
–40 °C to +85 °C
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ Max* Unit
LSBU
(Device
without
ECC)
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
LSBU
(Device with
ECC)
0
0.01
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical
2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [14, 15]
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
VOH
Output HIGH Voltage
for 3.3 V I/O, IOH = –4.0 mA
2.4
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
for 3.3 V I/O, IOL = 8.0 mA
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage[14]
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
VIL
Input LOW Voltage[14]
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Notes
14. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) of at least 200 ms. During this time VIH < VDD and VDDQ <VDD.


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