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CY7C1381KV33 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY7C1381KV33
Description  18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
Download  34 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1381KV33 Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *F
Page 2 of 34
Logic Block Diagram – CY7C1381KV33
(512K × 36)
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A[1:0]
DQs
DQP A
DQP B
DQP C
DQP D
A0, A1, A
ADV
CLK
ADSP
ADSC
BW D
BW C
BW B
BW A
BWE
CE1
CE2
CE3
OE
GW
SLEEP
DQ A,
DQP A
BYTE
WRITE REGISTER
DQ B,
DQP B
WRITE REGISTER
DQ C ,
DQP C
WRITE REGISTER
BYTE
WRITE REGISTER
DQ D,
DQP D
BYTE
WRITE REGISTER
DQ D,
DQP D
BYTE
WRITE REGISTER
DQ C ,
DQP C
WRITE REGISTER
DQ B,
DQP B
WRITE REGISTER
DQ A,
DQP
BYTE
WRITE REGISTER
Logic Block Diagram – CY7C1381KVE33
(512K × 36)
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A[1:0]
ZZ
DQs
DQPA
DQPB
DQPC
DQPD
A0, A1, A
ADV
CLK
ADSP
ADSC
BWD
BWC
BWB
BWA
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQA,
DQPA
BYTE
WRITE REGISTER
DQB,
DQPB
BYTE
WRITE REGISTER
DQC,
DQPC
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQD,
DQPD
BYTE
WRITE REGISTER
DQD,
DQPD
BYTE
WRITE REGISTER
DQC,
DQPC
BYTE
WRITE REGISTER
DQB,
DQPB
BYTE
WRITE REGISTER
DQA,
DQPA
BYTE
WRITE REGISTER
ECC
DECODER
ECC
ENCODER


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