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CY7C1381KV33 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1381KV33 Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 34 page 
CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Document Number: 001-97888 Rev. *F Page 8 of 34 MODE Input Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull-up. VDD Power Supply Power supply inputs to the core of the device. VDDQ I/O Power Supply Power supply for the I/O circuitry. VSS Ground Ground for the core of the device. VSSQ I/O Ground Ground for the I/O circuitry. TDO JTAG Serial Output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin can be left unconnected. This pin is not available on TQFP packages. TDI JTAG Serial Input Synchronous Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available on TQFP packages. TMS JTAG Serial Input Synchronous Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. VSS/DNU Ground/DNU This pin can be connected to ground or can be left floating. Pin Definitions (continued) Name I/O Description |
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