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CY7C1381KV33 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part No. CY7C1381KV33
Description  18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY7C1381KV33 Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *F
Page 7 of 34
Pin Definitions
Name
I/O
Description
A0, A1, A
Input
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB,
BWC, BWD
Input
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
GW
Input
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
CLK
Input
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
Input
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
Input
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
Input
Asynchronou
s
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
the address in a burst cycle.
ADSP
Input
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
Input
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
Input
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
ZZ
Input
Asynchronou
s
ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data
integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull down.
DQs
I/O
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/O
Synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.


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