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CY7C1381KV33 Datasheet(PDF) 33 Page - Cypress Semiconductor |
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CY7C1381KV33 Datasheet(HTML) 33 Page - Cypress Semiconductor |
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33 / 34 page 
CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Document Number: 001-97888 Rev. *F Page 33 of 34 Document History Page Document Title: CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC) Document Number: 001-97888 Rev. ECN No. Orig. of Change Submission Date Description of Change *C 4983482 DEVM 10/26/2015 Changed status from Preliminary to Final. *D 5085859 DEVM 01/14/2016 Post to external web. *E 5333612 PRIT 07/01/2016 Updated Truth Table: Updated details in “CE3” column corresponding to fifth row of “Deselected Cycle, Power Down”. Updated Neutron Soft Error Immunity: Updated values in “Typ” and “Max” columns corresponding to LSBU (Device without ECC) parameter. Updated to new template. *F 6073260 CNX 02/16/2018 Updated Package Diagrams: spec 51-85050 – Changed revision from *E to *G. Updated to new template. |
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