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CY7C1049G-10ZSXIT Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C1049G-10ZSXIT Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 19 page CY7C1049G CY7C1049GE Document Number: 001-95412 Rev. *E Page 9 of 19 AC Switching Characteristics Over the operating range of –40 C to 85 C Parameter [14] Description 10 ns 15 ns Unit Min Max Min Max Read Cycle tRC Read cycle time 10 – 15 – ns tAA Address to data / ERR valid – 10 – 15 ns tOHA Data / ERR hold from address change 3 – 3 – ns tACE CE LOW to data / ERR valid – 10 – 15 ns tDOE OE LOW to data / ERR valid – 4.5 – 8 ns tLZOE OE LOW to low impedance[15] 0 –0– ns tHZOE OE HIGH to HI-Z[15] – 5–8 ns tLZCE CE LOW to low impedance[15] 3 –3– ns tHZCE CE HIGH to HI-Z[15] – 5–8 ns tPU CE LOW to power-up[16, 17] 0 –0– ns tPD CE HIGH to power-down[16, 17] –10–15 ns Write Cycle [17, 18] tWC Write cycle time 10 – 15 – ns tSCE CE LOW to write end 7 – 12 – ns tAW Address setup to write end 7 – 12 – ns tHA Address hold from write end 0– 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low impedance[15] 3 –3– ns tHZWE WE LOW to HI-Z[15] – 5–8 ns Notes 14. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V).Testconditionsforthereadcycleuseoutputloading,asshowninpart(a)ofFigure4onpage7,unlessspecifiedotherwise. 15. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 4 on page 7. Transition is measured 200 mV from steady state voltage. 16. These parameters are guaranteed by design and are not tested. 17. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 18. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tDS and tHZWE. |
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