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CY7C1069GE30-10ZSXI Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C1069GE30-10ZSXI Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 20 page Document Number: 001-81539 Rev. *J Page 10 of 20 CY7C1069G CY7C1069GE AC Switching Characteristics Over the Operating Range of –40 C to 85 C Parameter [16] Description 10 ns 15 ns Unit Min Max Min Max Read Cycle tPOWER VCC stable to first access [17, 18] 100.0 – 100.0 – s tRC Read cycle time 10.0 – 15.0 – ns tAA Address to data / ERR valid – 10.0 – 15.0 ns tOHA Data / ERR hold from address change 3.0 – 3.0 – ns tACE CE LOW to data / ERR valid [19] – 10.0 – 15.0 ns tDOE OE LOW to data / ERR valid – 5.0 – 8.0 ns tLZOE OE LOW to low Z [20, 21, 22] 0– 1.0 – ns tHZOE OE HIGH to high Z [20, 21, 22] – 5.0 – 8.0 ns tLZCE CE LOW to low Z [19, 20, 21, 22] 3.0– 3.0– ns tHZCE CE HIGH to high Z [19, 20, 21, 22] – 5.0 – 8.0 ns tPU CE LOW to power-up [18, 19] 0 –0– ns tPD CE HIGH to power-down [18, 19] – 10.0 – 15.0 ns Write Cycle [23, 24] tWC Write cycle time 10.0 – 15.0 – ns tSCE CE LOW to write end [19] 7.0 – 12.0 – ns tAW Address setup to write end 7.0 – 12.0 – ns tHA Address hold from write end 0– 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7.0 – 12.0 – ns tSD Data setup to write end 5.0 – 8.0 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low Z [20, 21, 22] 3.0– 3.0– ns tHZWE WE LOW to high Z [20, 21, 22] – 5.0 – 8.0 ns Notes 16. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in part (a) of Figure 5 on page 8, unless specified otherwise. 17. tPOWER gives minimum amount of time that the power supply is at stable VCC until first memory access is performed. 18. These parameters are guaranteed by design and are not tested. 19. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 20. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 8. Transition is measured 200 mV from steady state voltage. 21. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 22. Tested initially and after any design or process changes that may affect these parameters. 23. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 24. The minimum write pulse width for write cycle No.2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. |
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