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CY7C1062G30-10BGXI Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1062G30-10BGXI
Description  16-Mbit (512 K words 횞 32 bits) Static RAM with Error-Correcting Code (ECC)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1062G30-10BGXI Datasheet(HTML) 9 Page - Cypress Semiconductor

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Document Number: 001-81609 Rev. *G
Page 9 of 20
CY7C1062G
CY7C1062GE
AC Switching Characteristics
Over the Operating Range of –40
C to 85 C
Parameter [13]
Description
10 ns
15 ns
Unit
Min
Max
Min
Max
Read Cycle
tPOWER
VCC (stable) to the first access[14, 15]
100.0
100.0
s
tRC
Read cycle time
10.0
15.0
ns
tAA
Address to data / ERR valid
10.0
15.0
tOHA
Data / ERR hold from address change
3.0
3.0
tACE
CE LOW to data / ERR valid [16]
–10.0–15.0
tDOE
OE LOW to data / ERR valid
5.0
8.0
tLZOE
OE LOW to low Z [17, 18]
0.0–
1.0–
tHZOE
OE HIGH to high Z [17, 18]
–5.0–8.0
tLZCE
CE LOW to low Z [16, 17, 18]
3.0–
3.0–
tHZCE
CE HIGH to high Z [16, 17, 18]
–5.0–8.0
tPU
CE LOW to power-up [15, 16]
0.0–
0.0–
tPD
CE HIGH to power-down [15, 16]
–10.0–15.0
tDBE
Byte enable to data valid
5.0
8.0
tLZBE
Byte enable to low Z
0.0
1.0
tHZBE
Byte disable to high Z
6.0
8.0
Write Cycle [19, 20]
tWC
Write cycle time
10.0
15.0
ns
tSCE
CE LOW to write end [16]
7.0
12.0
tAW
Address setup to write end
7.0
12.0
tHA
Address hold from write end
0.0
0.0
tSA
Address setup to write start
0.0
0.0
tPWE
WE pulse width
7.0
12.0
tSD
Data setup to write end
5.0
8.0
tHD
Data hold from write end
0.0
0.0
tLZWE
WE HIGH to low Z [17, 18]
3.0–
3.0–
tHZWE
WE LOW to high Z [17, 18]
–5.0–8.0
tBW
Byte Enable to write end
7.0
12.0
Notes
13. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 7, unless specified otherwise.
14. tPOWER gives minimum amount of time that the power supply is at stable Vcc until first memory access is performed.
15. These parameters are guaranteed by design and are not tested.
16. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3 HIGH.
17. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 7. Transition is measured 200 mV from steady
state voltage.
18. Tested initially and after any design or process changes that may affect these parameters.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
20. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE Low) should be sum of tHZWE and tSD.


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