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CY7C1061GN30-10ZSXIT Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1061GN30-10ZSXIT
Description  16-Mbit (1M words 횞 16 bit) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1061GN30-10ZSXIT Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY7C1061GN/CY7C10612GN
Document Number: 001-93680 Rev. *C
Page 9 of 21
AC Switching Characteristics
Over the Operating Range
Parameter [12]
Description
-10
-15
Unit
Min
Max
Min
Max
Read Cycle
tpower
VCC(typical) to the first access [13]
100
100
s
tRC
Read cycle time
10
15
ns
tAA
Address to data valid
10
15
ns
tOHA
Data hold from address change
3
3
ns
tACE
CE1 LOW/CE2 HIGH to data valid
10
15
ns
tDOE
OE LOW to data valid
5
8
ns
tLZOE
OE LOW to low Z [14]
0
–1–
ns
tHZOE
OE HIGH to high Z [14, 15]
5–8
ns
tLZCE
CE1 LOW/CE2 HIGH to low Z [14]
3
–3–
ns
tHZCE
CE1 HIGH/CE2 LOW to high Z [14, 15]
5–8
ns
tPU
CE1 LOW/CE2 HIGH to power-up [16]
0
–0–
ns
tPD
CE1 HIGH/CE2 LOW to power-down [16]
–10–15
ns
tDBE
Byte enable to data valid
5
8
ns
tLZBE
Byte enable to low Z
0
1
ns
tHZBE
Byte disable to high Z
6
8
ns
Write Cycle [17, 18]
tWC
Write cycle time
10
15
ns
tSCE
CE1 LOW/CE2 HIGH to write end[19]
7–
12
ns
tAW
Address setup to write end
7
12
ns
tHA
Address hold from write end
0–
0–
ns
tSA
Address setup to write start
0
0
ns
tPWE
WE pulse width
7
12
ns
tSD
Data setup to write end
5
8
ns
tHD
Data hold from write end
0
0
ns
tLZWE
WE HIGH to low Z [14]
3
–3–
ns
tHZWE
WE LOW to high Z [14, 15]
5–8
ns
tBW
Byte Enable to End of Write
7–
12
ns
Notes
12. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 7 on page 7, unless specified otherwise.
13. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Hi-Z, Lo-Z transition is measured 200 mV from steady state
voltage.
16. These parameters are guaranteed by design and are not tested.
17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be
LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal
that terminates the write.
18. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
19. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.


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