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BCM5228 Datasheet(PDF) 1 Page - Broadcom Corporation. |
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BCM5228 Datasheet(HTML) 1 Page - Broadcom Corporation. |
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1 / 100 page  5228-DS09-405-R 16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 7/12/04 Data Sheet BCM5228 10/100BASE-TX/FX Octal- Φ™ Transceiver Figure 1: Functional Block Diagram G EN ER AL DE SC RI PTI O N F EA TU RE S The BCM5228 is an octal 10 /100BASE-TX/FX transceiver targeted at Fast Ethernet switches. The device contains eight full-duplex 10BASE-T/100BASE- TX/FX Fast Ethernet transceivers, each of which perform all of the physical layer interface functions for 10BASE-T Ethernet on Category 3, 4, or 5 unshielded twisted-pair (UTP) cable and 100BASE-TX Fast Ethernet on Category 5 UTP cable. The 100BASE-FX is supported at each port through the use of external fiber- optic transmit and receive devices. The BCM5228 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase locked loops, line drivers, encoders, decoders, and the required support circuitry into a single monolithic CMOS chip. The BCM5228 complies with the IEEE 802.3 specification, including the auto-negotiation subsections. The effective use of digital technology in the BCM5228 design results in robust performance over a broad range of operating scenarios. Problems inherent to mixed- signal implementations (such as analog offset and on- chip noise) are eliminated by employing field-proven digital adaptive equalization and digital clock recovery techniques. • 10BASE-T/100BASE-TX/FX IEEE 802.3u compliant • Single-chip octal physical interface-RMII to magnetics • Reduced Media Independent Interface (RMII) • Option-Serial Media Independent Interface (SMII) • Option-Source Synchronous SMII (S3MII) • Fully integrated digital adaptive equalizers • 125-MHz clock generator and timing recovery • On-chip multimode transmit waveshaping • Edge-rate control eliminates external filters • Integrated baseline wander correction • HP Auto-MDIX • Cable length indication • Cable noise level indication • IEEE 802.3 υ-compliant auto-negotiation • Shared MII management interface up to 25 Mbps • Serial LED status pins • Programmable parallel LED pins • Interrupt output capability • Loopback mode for diagnostics • IEEE 1149.1 (JTAG) and NAND chain ICT support • Low-power, dual-supply 2.5V/3.3V CMOS technology • Compatible with 2.5V/3.3V I/O • 208-pin PQFP and 256-pin FPBGA packages A PP LIC AT I O NS • Fast Ethernet switches MII MII Equalizer Auto-Negotiation LED/INT Clock Bias Registers Mgmt Control Correction /Link Integrity Generator Generator Wander Baseline 8 RXD{1:8} MDC MDIO MODES/CONTROLS TD± {1:8} RD± {1:8} REF_CLK Recovery Xmt DAC CRS/Link Detection ADC LED2{1:8} SSSMII_DIS/SLED_CLK Multimode JTAG Test Logic 5 JTAG Digital Adaptive 10BASE-T PCS 100BASE-X PCS Drivers Clock 13 8 INTR/SLED_DO LED1{1:8} 8 8 TXD{1:8} RDAC SSYNC SSSMII_TXC SSSMII_RSYNC Auto- MDIX SSSMII_RXC |
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