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S79FL512S Datasheet(PDF) 11 Page - Cypress Semiconductor |
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S79FL512S Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 111 page  Document Number: 002-00518 Rev. *D Page 11 of 111 S79FL256S/S79FL512S Figure 3. Dual-Quad SPI DDR Modes Supported 3.2 Command Protocol All communication between the host system and S25FL-S memory devices is in the form of units called commands. All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All instruction, address, and data information is transferred serially between the host system and memory device. Quad Input / Output (I/O) commands provide an address sent from the host as four bit (nibble) groups on IO0, IO1, IO2, IO3 and repeated on IO4, IO5, IO6, IO7, then followed by dummy cycles. Data is returned to the host as byte on IO0 - IO7. This is referenced as 2-8-8 for Quad I/O command protocols. Commands are structured as follows: Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host driving the Chip Select (CS#) signal low throughout a command. The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory. Each command begins with an 8-bit (byte) instruction. The instruction is always presented only as a single bit serial sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising edge. The instruction selects the type of information transfer or device operation to be performed. The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands. Quad I/O read instructions send an instruction modifier called Continuous Read mode bits, following the address, to indicate whether the next command will be of the same type with an implied, rather than an explicit, instruction. These mode bits initiate or end the continuous read mode. In continuous read mode, the next command thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands. CPOL=0_CPHA=0_SCLK CPOL=1_CPHA=1_SCLK CS# Transfer_Phase IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 Inst. 7 Inst. 0 A28 A24 A0 M4 M0 DLP. DLP. D0 D1 A29 A25 A1 M5 M1 DLP. DLP. D0 D1 A30 A26 A2 M6 M2 DLP. DLP. D0 D1 A31 A27 A3 M7 M3 DLP. DLP. D0 D1 Inst. 7 Inst. 0 A28 A24 A0 M4 M0 DLP. DLP. D0 D1 A29 A25 A1 M5 M1 DLP. DLP. D0 D1 A30 A26 A2 M6 M2 DLP. DLP. D0 D1 A31 A27 A3 M7 M3 DLP. DLP. D0 D1 Dummy / DLP Address Mode Instruction |
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