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S79FL256S Datasheet(PDF) 6 Page - Cypress Semiconductor |
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S79FL256S Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 111 page  Document Number: 002-00518 Rev. *D Page 6 of 111 S79FL256S/S79FL512S Hardware Interface Serial Peripheral Interface with Multiple Input / Output (SPI-MIO) Dual-Quad Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large number of signal connections and larger package size. The large number of connections increase power consumption due to so many signals switching and the larger package increases cost. The S25FL-S Dual-Quad SPI devices reduce the number of signals for connection to the host system by serially transferring all control, address, and data information over 10 signals. This reduces the cost of the memory package, reduces signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features. The S25FL-S Dual-Quad SPI devices use the industry standard single bit Serial Peripheral Interface (SPI) using two Quad SPI devices in each package (Quad SPI-1 and Quad SPI-2). This interface is called Dual-Quad and enables support of Byte wide (8 bit) serial transfers. There is one package option available for S79FL256S/S79FL512S: 16-pin SOIC package For documentation simplicity, all AC timings and waveforms and DC specification are defined using single CS# (Chip Select) and SCK (Serial Clock) signals. For S79FL256S/S79FL512S, the CS# signals and the SCK signals for Quad SPI-1 and Quad SPI-2 are internally tied together in the package. 2. Signal Descriptions 2.1 Input/Output Summary Table 1. Dual-Quad Input/Output Descriptions Signal Name Type Description RESET# Input Hardware Reset: Low = device resets and returns to standby state, ready to receive a command. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used. SCK Input Serial Clock CS# Input Chip Select IO0 I/O I/O 0 for Quad SPI-1 IO1 I/O I/O 1 for Quad SPI-1 IO2 I/O I/O 2 for Quad SPI-1 IO3 I/O I/O 3 for Quad SPI-1 IO4 I/O I/O 0 for Quad SPI-2 IO5 I/O I/O 1 for Quad SPI-2 IO6 I/O I/O 2 for Quad SPI-2 IO7 I/O I/O 3 for Quad SPI-2 VCC Supply Core Power Supply VSS Supply Ground NC Unused Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal connected to a NC pin must not have voltage levels higher than the VCC absolute maximum (Supply Voltage). RFU Reserved Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use for the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices. |
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