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S71KS512SC0 Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # S71KS512SC0
Description  HyperFlash??and HyperRAM?줞ulti-Chip Package 1.8V/3V
Download  14 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S71KS512SC0 Datasheet(HTML) 8 Page - Cypress Semiconductor

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Document Number: 002-03902 Rev. *D
Page 8 of 14
SUPPLEMENT
S71KS512SC0
S71KL256SC0
S71KL512SC0
Electrical Specifications
For the general description of the HyperBus interface electrical
specifications, refer to the HyperBus Specification. The following
section describes HyperFlash device dependent aspects of
electrical specifications.
Absolute Maximum Ratings
Ambient Temperature with Power Applied:
65 °C to +105 °C
DC Characteristics
Only one memory may have its chip select active (Low) at any
point in time. For each of the conditions below refer to the Hyper-
Flash and HyperRAM datasheets for the most accurate infor-
mation:
Active core read or write current will be that of the selected
device plus the standby current of the non-selected device. But,
the added standby current is generally not significant as it is
less than 300
A.
Active IO read current will be that of the selected device.
Active clock stop current will be that of the selected device plus
the standby current of the non-selected device. But, the added
standby current is generally not significant as it is less than
300
A.
Program or erase current will be that of the HyperFlash device.
Note however, that program and erase operations are long time
frame events that extend beyond the duration of a HyperFlash
chip select period. Thus, if the HyperRAM is selected for read
or write during an on going HyperFlash program or erase
operation, the active current will be the sum of the HyperFlash
program or erase operation and the HyperRAM read or write
current.
Standby current, when neither memory is selected and no
embedded flash operation is in progress, is the sum of the
memory standby currents.
Deep Power Down (DPD) current, is the sum of the memory
DPD currents.
Power On Reset (POR) current is the sum of the memory
standby currents.
Input leakage current is the sum of the memory input leakage
currents.
For reference purpose, Table 3 aids in the estimation of the
above operating conditions current consumption. However, refer
to the HyperFlash and HyperRAM datasheets for the most
accurate information.


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