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S34MS01G2 Datasheet(PDF) 56 Page - Cypress Semiconductor |
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S34MS01G2 Datasheet(HTML) 56 Page - Cypress Semiconductor |
56 / 74 page Document Number: 002-03238 Rev. *E Page 56 of 74 S34MS01G2 S34MS02G2 S34MS04G2 6.24 Multiplane Cache Program — S34MS02G2 and S34MS04G2 Figure 6.30 Multiplane Cache Program Notes: 1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used. 2. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices. CLE ALE CE# RE# R/B# I/Ox WE# Column Address Row Address tWB tWC Column Address Row Address tCBSYW 1 1 tDBSY 80h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 81h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 15h Din N Din M 11h Din N Din M Column Address Row Address tWC Column Address Row Address tPROG tDBSY 11h Din N Din M 80h 81h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 10h Din N Din M tWB tADL tADL tWB Status 70h 80h Address Input Data Input 11h 81h Address Input Data Input 15h Command Input A13~A17: Fixed ‘Low’ A18: Fixed ‘Low’ A19~A31: Fixed ‘Low’ A13~A17: Valid A18: Fixed ‘High’ A19~A31: Valid tDBSY Return to 1 Repeat a max of 63 times 80h Address Input Data Input 11h 81h Address Input Data Input 10h Command Input A13~A17: Fixed ‘Low’ A18: Fixed ‘Low’ A19~A31: Fixed ‘Low’ A13~A17: Valid A18: Fixed ‘High’ A19~A31: Valid tDBSY tPROG tCBSYW RY/BY# RY/BY# 1 1 CLE ALE CE# RE# R/B# I/Ox WE# Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 |
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