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IDT74LVCH16374A Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT74LVCH16374A
Description  3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74LVCH16374A Datasheet(HTML) 1 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
IDT74LVCH16374A
3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 1999 Integrated Device Technology, Inc.
DSC-4643/2
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4
µµµµµ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
IDT74LVCH16374A
DESCRIPTION
The LVCH16374A 16-bit edge-triggered D-type register is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
commonclock.Flow-throughorganizationofsignalpinssimplifieslayout.All
inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH16374A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/5V
supply system.
The LVCH16374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 16-BIT
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS,
5V TOLERANT I/O AND BUS-HOLD
1
OE
1
CLK
1
D1
1
Q1
TO SEVEN OTHER CHANNELS
2
OE
2
CLK
2
D1
2
Q1
1
48
47
2
24
25
36
13
C1
1
D
1
D
C1
TO SEVEN OTHER CHANNELS


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