1:10 Clock Fanout Buffer with Output Enable
COMLINK™ SERIES
CY2CC1910
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07347 Rev. *B
Revised December 26, 2002
Features
• Low-voltage operation
• Full-range support:
— 3.3V
— 2.5V
— 1.8V
• 1:10 fanout
• Drives either a 50-Ohm or 75-Ohm load
• Over voltage tolerant input hot swappable
• Low-input capacitance
• Low-output skew
• Low-propagation delay
• Typical (tpd < 4 ns)
• High-speed operation:
— 100 MHz@1.8V
— 200 MHz@2.5V/3.3V
• Industrial versions available
• Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
Cypress employs unique AVCMOS-type outputs VOI™
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors; they also reduce noise overall.
Pin Description
Pin Number
Pin Name
Pin Description
1, 7, 8, 12, 13, 17, 20, 24
GND
Ground
Power
3,10,15,22
VDD
Power Supply
Power
5
OE#
Output Enable
LVTTL/LVCMOS
6
IN
Input
LVTTL/LVCMOS
2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output
AVCMOS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24 pin SOIC/SSOP
GND
Q1
VDD
Q2
GND
Q3
Q4
GND
Q5
VDD
Q6
GND
GND
Q10
Q9
OE#
IN
GND
GND
Q8
VDD
Q7
GND
VDD
16
11
14
18
23
19
21
9
4
2
6
OUTPUT (AVCMOS)
OE#
5
IN
Q5
Q7
Q6
Q4
Q1
Q3
Q2
Q8
Q9
Q1 0
GN D
VDD
1,12,13
17,24
3,10
15,22
AVCMOS
AVCMOS
Block Diagram
Pin Configuration
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