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LMX8410L Datasheet(PDF) 3 Page - Texas Instruments |
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LMX8410L Datasheet(HTML) 3 Page - Texas Instruments |
3 / 63 page CE VBIAS_VCO2 VBIAS_VCO1 OSCINP CSB GND RF VCC_RF GND SYNC GND VCC_DIG OSCINM VREG_OSCIN MUXOUT VCC_CP SDI VCC_IFQ NC VCC_RF GND NC VCC_IFI VCM_IN 47 48 46 45 44 43 42 41 40 39 38 37 11 12 10 9 8 7 6 5 4 3 2 1 14 13 15 16 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 33 34 35 36 DAP 49 3 LMX8410L www.ti.com SNAS730 – MARCH 2018 Product Folder Links: LMX8410L Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 5 Pin Configuration and Functions RGZ Package 48-Pin QFN Top View Pin Functions PIN I/O DESCRIPTION NAME NAME 1 CE Input Chip Enable input. Active HIGH powers on the device. 2 VBIAS_VCO2 Bypass VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using external LO, this pin must be floated. 3 VBIAS_VCO1 Bypass VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using external LO, this pin must be floated. 4 GND Ground VCO ground. VBIAS pin capacitors must bypass to this point. 5 SYNC Input Trigger pin for synchronizing multiple devices. If using external LO, tie this pin to GND. 6 GND Ground Digital ground. VCC_DIG bypass capacitors must bypass to this point. 7 VCC_DIG Supply Digital supply. TI recommends connecting 0.1-µF capacitor to digital ground. 8 OSCINP Input Reference input clock (+). High input impedance. Requires connecting series capacitor (0.1 µF recommended). If using external LO, tie this pin to GND. 9 OSCINM Input Reference input clock (–). High input impedance. Requires connecting series capacitor (0.1 µF recommended). If using external LO, tie this pin to GND. 10 VREG_OSCIN Bypass Internal LDO output. Requires connecting 1-µF capacitor to digital ground. Place close to pin. If using external LO, this pin should be floated. 11 MUXOUT Output Readback or lock detect output. Pin mode configured by internal register settings. |
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