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MB95F856K Datasheet(PDF) 66 Page - Cypress Semiconductor |
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MB95F856K Datasheet(HTML) 66 Page - Cypress Semiconductor |
66 / 172 page Document Number: 002-09305 Rev. *C Page 66 of 172 PRELIMINARY MB95F856K, MB95F866K, MB95F876K 3. Port 6 registers ■ Port 6 register functions ■ Correspondence between registers and pins for port 6 4. Port 6 operations ■ Operation as an output port ❐ A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. ❐ When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. ❐ If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ❐ Reading the PDR6 register returns the PDR6 register value. ■ Operation as an input port ❐ A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. ❐ When using a pin shared with the touch input function as an input port, set the bit in the touch input disable register 0 (TIDR0) corresponding to that pin to “1”. ❐ If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. ❐ Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. ■ Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. As for a pin shared with the touch input function, its port input is disabled because the TIDR0 register is initialized to “0”. ■ Operation in stop mode and watch mode ❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. ❐ When the stop enable bit in the TS prescaler control register (PSC:STPE) is set to “1”, the TS can operate in stop mode or watch mode, the touch input is enabled and is not blocked. The TS wakes up in stop mode or watch mode provided that the TINT (touch interrupt) and the GINT (general interrupt) are set to enable the TS to wake up in stop mode or watch mode. ❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. ■ Operation as a touch input pin Set the bit in the DDR6 register corresponding to the touch input pin to “0”, the bit in the TIDR0 register corresponding to the same pin to “0”, and the bit in the PUL6 register corresponding to the same pin to “0”. ■ Operation of the pull-up register Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register. Register abbreviation Data Read Read by read-modify-write (RMW) instruction Write PDR6 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level. DDR6 0 Port input enabled 1 Port output enabled PUL6 0 Pull-up disabled 1 Pull-up enabled TIDR0 0 Touch input or reference input enabled 1 Port input enabled Pin name Correspondence between related register bits and pins P67 P66 P65 - P63 - - - PDR6 bit7 bit6 bit5 - bit3 -- - DDR6 PUL6 TIDR0 bit7 bit6 bit5 bit3 |
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