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ADS8380 Datasheet(PDF) 3 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part No. ADS8380
Description  18-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE
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Maker  BURR-BROWN [Burr-Brown (TI)]
Homepage  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

ADS8380 Datasheet(HTML) 3 Page - Burr-Brown (TI)

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SPECIFICATIONS
ADS8380
SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004
At –40
°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, f
SAMPLE = 600 kHz,
unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down, see
Table 2.)
ADS8380IB
ADS8380I
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
ANALOG INPUT
Full-scale
+IN – (–IN)
0
Vref
0
Vref
V
input voltage(1)
+IN
–0.2
Vref + 0.2
-0.2
Vref + 0.2
Absolute input voltage
V
–IN
–0.2
0.2
-0.2
0.2
Sampling capacitance
(measured from
±IN to
40
40
pF
AGND)
Input leakage current
1
1
nA
SYSTEM PERFORMANCE
Resolution
18
18
Bits
No missing codes
18
17
Bits
Quiet zones observed
–4
±2
4
–6
6
LSB
INL
Integral linearity(2)(3)(4)
(18 bit)
Quiet zones not observed
±2.75
Quiet zones observed
–1
±0.75
1.5
–2
2.5
LSB
DNL
Differential linearity(3)
(18 bit)
Quiet zones not observed
±1.5
EO
Offset error (3)
–0.75
±0.4
0.75
–1.5
1.5
mV
EG
Gain error(3)(5)
–0.075
0.075
-0.1
0.1
%FS
At DC
80
80
Common-mode rejection
[+IN – (–IN)] = Vref/2 with
CMRR
dB
ratio
50 mVp-p common mode
55
55
signal at 1 MHz
Noise
At 0 V analog input
40
40
µV RMS
DC Power supply rejec-
PSRR
At full scale analog input
55
55
dB
tion ratio
SAMPLING DYNAMICS
Conversion time
1.16
1.16
µs
Acquisition time
0.50
1000
0.50
1000
µs
Throughput rate
600
600
kHz
Aperture delay
10
10
ns
Aperture jitter
12
12
ps RMS
Step response
(6)
400
400
ns
Overvoltage recovery
400
400
ns
(1)
Ideal input span; does not include gain or offset error.
(2)
LSB means least significant bit.
(3)
Measured using analog input circuit in Figure 51 and digital stimulus in Figure 56 and Figure 57 and reference voltage of 4.096 V.
(4)
This is endpoint INL, not best fit.
(5)
Measured using external reference source so does not include internal reference voltage error or drift.
(6)
Defined as sampling time necessary to settle an initial error of Vref on the sampling capacitor to a final error of 1 LSB at 18-bit level.
Measured using the input circuit in Figure 51.
3


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