Electronic Components Datasheet Search |
|
SN74AUP1G79DBVTE4 Datasheet(PDF) 1 Page - Texas Instruments |
|
SN74AUP1G79DBVTE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 15 page SN74AUP1G79 LOW POWER SINGLE POSITIVEEDGETRIGGERED DTYPE FLIPFLOP SCES592A − JULY 2004 − REVISED SEPTEMBER 2005 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Available in the Texas Instruments NanoStar and NanoFree Packages D Low Static-Power Consumption; ICC = 0.9 µA Max D Low Dynamic-Power Consumption; Cpd = 3 pF Typ at 3.3 V D Low Input Capacitance; Ci = 1.5 pF Typ D Low Noise − Overshoot and Undershoot <10% of VCC D Ioff Supports Partial-Power-Down Mode Operation D Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V) D Wide Operating VCC Range of 0.8 V to 3.6 V D Optimized for 3.3-V Operation D 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation D tpd = 3.6 ns Max at 3.3 V D Suitable for Point-to-Point Applications D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) D ESD Protection Exceeds ±5000 V With Human-Body Model DBV OR DCK PACKAGE (TOP VIEW) 1 2 3 5 4 D CLK GND VCC Q 3 2 1 4 5 GND CLK D Q VCC YEP OR YZP PACKAGE (BOTTOM VIEW) description /ordering information The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2). Figure 1. AUP − The Lowest-Power Family AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% −0.5 0 0.5 1 1.5 2 2.5 3 3.5 05 10 15 20 25 30 35 40 45 Figure 2. Excellent Signal Integrity Time − ns † AUP1G08 data at C L = 15 pF Output Input Switching Characteristics at 25 MHz† This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. Copyright 2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Similar Part No. - SN74AUP1G79DBVTE4 |
|
Similar Description - SN74AUP1G79DBVTE4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |