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CY8C5287AXI-LP095 Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C5287AXI-LP095 Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 114 page  PSoC® 5LP: CY8C52LP Family Datasheet Document Number: 001-84933 Rev. *L Page 11 of 114 Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance 3. Pin Descriptions IDAC0. Low resistance output pin for high IDAC. Extref0, Extref1. External reference input to the analog system. SAR0 EXTREF, SAR1 EXTREF. External references for SAR ADCs GPIO. General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[6]. I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. Ind. Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25-MHz crystal oscillator pin. nTRST. Optional JTAG Test Reset programming and debug port connection to reset the JTAG connection. SIO. Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK. Serial wire debug clock programming and debug port connection. SWDIO. Serial wire debug Input and output programming and debug port connection. TCK. JTAG test clock programming and debug port connection. TDI. JTAG test data In programming and debug port connection. TDO. JTAG test data out programming and debug port connection. TMS. JTAG test mode select programming and debug port connection. TRACECLK. Cortex-M3 TRACEPORT connection, clocks TRACEDATA pins. TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections, output data. SWV. Single wire viewer output. USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. VBOOST. Power sense connection to boost pump. VBAT. Battery supply to boost pump. VCCA. Output of the analog core regulator or the input to the analog core. Requires a 1uF capacitor to VSSA. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. For details see “Power System” section on page 26. VD D D VSSD V DDA VSSA VSSD Plan e VS SA Plan e Notes 6. GPIOs with opamp outputs are not recommended for use with CapSense. |
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