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CY8C5266AXI-LP132 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY8C5266AXI-LP132 Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 114 page  PSoC® 5LP: CY8C52LP Family Datasheet Document Number: 001-84933 Rev. *L Page 9 of 114 Table 2-2 shows the pinout for the 99-pin CSP package. Since there are four VDDIO pins, the set of I/O pins associated with any VDDIO may sink up to 100 mA total, same as for the 100-pin and 68-pin devices. Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. The two pins labeled VDDD must be connected together. The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on page 26. The trace between the two VCCD pins should be as short as possible. The two pins labeled VSSD must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Table 2-2. CSP Pinout Ball Name Ball Name Ball Name Ball Name E5 P2[5] L2 VIO1 B2 P3[6] C8 VIO0 G6 P2[6] K2 P1[6] B3 P3[7] D7 P0[4] G5 P2[7] C9 P4[2] C3 P12[0] E7 P0[5] H6 P12[4] E8 P4[3] C4 P12[1] B9 P0[6] K7 P12[5] K1 P1[7] E3 P15[2] D8 P0[7] L8 P6[4] H2 P12[6] E4 P15[3] D9 P4[4] J6 P6[5] F4 P12[7] A1 NC F8 P4[5] H5 P6[6] J1 P5[4] A9 NC F7 P4[6] J5 P6[7] H1 P5[5] L1 NC E6 P4[7] L7 VSSB F3 P5[6] L9 NC E9 VCCD K6 Ind G1 P5[7] A3 VCCA F9 VSSD L6 VBOOST G2 P15[6] A4 VSSA G9 VDDD K5 VBAT F2 P15[7] B7 VSSA H9 P6[0] L5 VSSD E2 VDDD B8 VSSA G8 P6[1] L4 XRES F1 VSSD C7 VSSA H8 P6[2] J4 P5[0] E1 VCCD A5 VDDA J9 P6[3] K4 P5[1] D1 P15[0] A6 VSSD G7 P15[4] K3 P5[2] D2 P15[1] B5 P12[2] F6 P15[5] L3 P5[3] C1 P3[0] A7 P12[3] F5 P2[0] H4 P1[0] C2 P3[1] C5 P4[0] J7 P2[1] J3 P1[1] D3 P3[2] D5 P4[1] J8 P2[2] H3 P1[2] D4 P3[3] B6 P0[0] K9 P2[3] J2 P1[3] B4 P3[4] C6 P0[1] H7 P2[4] G4 P1[4] A2 P3[5] A8 P0[2] K8 VIO2 G3 P1[5] B1 VIO3 D6 P0[3] |
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