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CY8C4248LQI-BL463 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY8C4248LQI-BL463 Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 48 page PRELIMINARY PSoC® 4: PSoC 4XX8_BLE Family Datasheet Document Number: 001-94624 Rev. *L Page 9 of 48 Fixed-Function Digital Timer/Counter/PWM Block The timer/counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. Serial Communication Blocks (SCB) PSoC 4XX8_BLE has two SCBs, each of which can implement an I2C, UART, or SPI interface. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI2C that creates a mailbox address range in the memory of PSoC 4XX8_BLE and effectively reduces the I2C communication to reading from and writing to an array in the memory. In addition, the block supports an 8-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I2C peripheral is compatible with I2C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. SCB1 is fully compliant with Standard mode (100 kHz), Fast mode (400 kHz), and Fast-Mode Plus (1 MHz) I2C signaling specifications when routed to GPIO pins P5[0] and P5[1], except for hot-swap capability during I2C active communication. The remaining GPIOs do not meet the hot-swap specification (VDD off; draw < 10-µA current) for Fast mode and Fast-Mode Plus, IOL Spec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 VDD) for Fast mode and Fast-Mode Plus, and minimum fall time spec for Fast mode and Fast-Mode Plus. ■ GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the I2C system. ■ The GPIO pins P5.0 and P5.1 are over-voltage tolerant but cannot be hot-swapped or powered up independent of the rest of the I2C system ■ Fast-Mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-Mode Plus specify minimum Fall times, which are not met with the GPIO cell; the Slow-Strong mode can help meet this spec depending on the bus load. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. Note that hardware handshaking is not supported. This is not commonly used and can be implemented with a UDB-based UART in the system, if required. SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and supports an EzSPI mode in which the data interchange is reduced to reading and writing an array in memory. GPIO PSoC 4XX8_BLE has 36 GPIOs. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL) ■ Pins 0 and 1 of Port 5 are overvoltage-tolerant pins ■ Individual control of input and output buffer enabling/disabling in addition to drive-strength modes ■ Hold mode for latching previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes) ■ Selectable slew rates for dV/dt-related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multi- plexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this and any pin may be routed to any UDB through the DSI network. Data output and pin-state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4XX8_BLE). |
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