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CY8C4125LQQ-483 Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C4125LQQ-483 Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 43 page  Document Number: 001-87220 Rev. *J Page 11 of 43 PSoC® 4: PSoC 4100 Family Datasheet The following is the pin-list for the PSoC 4100 (35-WLCSP). 35-Ball CSP Alternate Functions for Pins Pin Description Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4 D3 P2.2 sarmux.2 – – – – Port 2 Pin 2: gpio, lcd, csd, sarmux E4 P2.3 sarmux.3 – – – – Port 2 Pin 3: gpio, lcd, csd, sarmux E5 P2.4 sarmux.4 tcpwm0_p[1] – – – Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm E6 P2.5 sarmux.5 tcpwm0_n[1] – – – Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm E3 P2.6 sarmux.6 tcpwm1_p[1] – – – Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm E2 P2.7 sarmux.7 tcpwm1_n[1] – – – Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm E1 P3.0 – tcpwm0_p[0] scb1_uart_rx[0] scb1_i2c_scl[0] scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm, scb1 D2 P3.1 – tcpwm0_n[0] scb1_uart_tx[0] scb1_i2c_sda[0] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm, scb1 D1 P3.2 – tcpwm1_p[0] – swd_io[0] scb1_spi_clk[0] Port 3 Pin 2: gpio, lcd, csd, pwm, scb1, swd B7 VSS – – – – – Ground C1 P3.3 – tcpwm1_n[0] – swd_clk[0] scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm, scb1, swd C2 P3.4 – tcpwm2_p[0] - – scb1_spi_ssel_1 Port 3 Pin 4: gpio, lcd, csd, pwm, scb1 B1 P4.0 – – scb0_uart_rx scb0_i2c_scl scb0_spi_mosi Port 4 Pin 0: gpio, lcd, csd, scb0 B2 P4.1 – – scb0_uart_tx scb0_i2c_sda scb0_spi_miso Port 4 Pin 1: gpio, lcd, csd, scb0 A2 P4.2 csd_c_mod – – – scb0_spi_clk Port 4 Pin 2: gpio, lcd, csd, scb0 A1 P4.3 csd_c_sh_tank – – – scb0_spi_ssel_0 Port 4 Pin 3: gpio, lcd, csd, scb0 C3 P0.0 comp1_inp – – – scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0, comp A5 P0.1 comp1_inn – – – scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0, comp A4 P0.2 comp2_inp – – – scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0, comp A3 P0.3 comp2_inn – – – – Port 0 Pin 3: gpio, lcd, csd, comp B3 P0.4 – – scb1_uart_rx[1] scb1_i2c_scl[1] scb1_spi_mosi[1] Port 0 Pin 4: gpio, lcd, csd, scb1 A6 P0.5 – – scb1_uart_tx[1] scb1_i2c_sda[1] scb1_spi_miso[1] Port 0 Pin 5: gpio, lcd, csd, scb1 B4 P0.6 – ext_clk – – scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk B5 P0.7 – – – wakeup scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup B6 XRES – – – – – Chip reset, active low A7 VCCD – – – – – Regulated supply, connect to 1µF cap or 1.8V C7 VDD – – – – – Supply, 1.8 - 5.5V C4 P1.0 ctb.oa0.inp tcpwm2_p[1] – – – Port 1 Pin 0: gpio, lcd, csd, ctb, pwm C5 P1.1 ctb.oa0.inm tcpwm2_n[1] – – – Port 1 Pin 1: gpio, lcd, csd, ctb, pwm |
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