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CYPD2103-14LHXIT Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CYPD2103-14LHXIT
Description  USB Type-C Port Controller
Download  33 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYPD2103-14LHXIT Datasheet(HTML) 4 Page - Cypress Semiconductor

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EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *L
Page 4 of 33
Figure 1. EZ-PD CCG2 Block Diagram
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in EZ-PD CCG2 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
EZ-PD CCG2 has four break-point (address) comparators and
two watchpoint (data) comparators.
Flash
The EZ-PD CCG2 device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS
access time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
CCG2
32-bit
AHB-Lite
CPU Subsystem
SRAM
4 KB
SRAM Controller
SROM
8 KB
SROM Controller
FLASH
32 KB
Read Accelerator
SPCIF
Deep Sleep
Active/Sleep
SWD/TC
NVIC, IRQMX
Cortex
M0
48 MHz
FAST MUL
System Interconnect (Single Layer AHB)
I/O Subsystem
12 x GPIOs, 2 x OVTs
Peripherals
Peripheral Interconnect (MMIO)
PCLK
High Speed I/O Matrix
USB-PD SS
Power Modes
DFT Logic
Test
DFT Analog
System Resources
Lite
Power
Clock
WDT
ILO
Reset
Clock Control
IMO
Sleep Control
PWRSYS
REF
POR
WIC
Reset Control
XRES
Pads, ESD


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