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ASM5I23S08AF-1H-16-TR Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation

Part # ASM5I23S08AF-1H-16-TR
Description  3.3V Zero Delay Buffer
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

ASM5I23S08AF-1H-16-TR Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation

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September 2005
ASM5P23S08A
rev 1.4
Notice: The information in this document is subject to change without notice.
3.3V ‘SpreadTrak’ Zero Delay Buffer
3 of 18
‘SpreadTrak’
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5P23S08A is designed so as not to filter off the
Spread Spectrum feature of the Reference input, assuming
it exists. When a zero delay buffer is not designed to pass
the Spread Spectrum feature through, the result is a
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output.
To close the feedback loop of the ASM5P23S08A, the FBK
pin can be driven from any of the eight available output
pins. The output driving the FBK pin will be driving a total
load of 7pF plus any additional load that it drives. The
relative loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph.
For applications requiring zero input-output delay, all
outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output-output skew, make sure to load
outputs equally.
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
0
-500
-1000
-1500
500
1000
1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)


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