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CY8C4245LQQ-483 Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY8C4245LQQ-483 Datasheet(HTML) 4 Page - Cypress Semiconductor |
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4 / 45 page  PSoC® 4: PSoC 4200 Family Datasheet Document Number: 001-87197 Rev. *J Page 4 of 45 Figure 2. Block Diagram The PSoC 4200 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The ARM Serial_Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4200 devices. The SWD interface is fully compatible with industry-standard third-party tools. With the ability to disable debug features, with very robust flash protection, and allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC 4200 family provides a level of security not possible with multi-chip application solutions or with microcontrollers. The debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Because all programming, debug, and test inter- faces are disabled when maximum device security is enabled, PSoC 4200 with device security enabled may not be returned for failure analysis. This is a trade-off the PSoC 4200 allows the customer to make. PSoC 4200 32-bit AH B-Lite CP U S ubs ys tem SR AM Up to 4 kB SR AM C ontroller ROM 4 kB ROM C ontroller FLASH Up to 32 kB R ead Accelerator D eep Sleep H ibernate Active /Sleep SWD N VIC, IR QM X Cortex M0 48 MH z FAST MU L System Interconnect (Single Layer AH B ) IO S ubs y stem 36x GPIOs Peripherals System R eso urces Pow er Clock WD T ILO Reset Clock Control D F T Logic Test IM O DF T Analog Sleep C ontrol PWR SYS REF POR LVD N VLatches BOD WIC Reset Control XRES Peripheral Interconnect (MMIO ) PC LK Port Interfa ce & D igita l System Intercon nect(D SI) Programmable Digital x4 UD B ... UDB Pow er Modes CTBm SM X SAR AD C (12-bit) x1 Programmable Analog x1 2x OpAm p High Spe ed I/O Matrix |
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