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CY8C4248FNI-BL543 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY8C4248FNI-BL543
Description  Programmable System-on-Chip (PSoC짰)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C4248FNI-BL543 Datasheet(HTML) 7 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 4: PSoC 4XX8 BLE 4.2
Family Datasheet
Document Number: 002-09848 Rev. *B
Page 7 of 47
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion (up to 806 Ksps for the
PSoC 41X8_BLE derivatives).
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice of three internal voltage references, VDD, VDD/2, and
VREF (nominally 1.024 V), as well as an external reference
through a GPIO pin. The Sample-and-Hold (S/H) aperture is
programmable; it allows the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling
time, to be relaxed if required. System performance will be 65 dB
for true 12-bit precision provided appropriate references are
used and system noise levels permit it. To improve the perfor-
mance in noisy conditions, it is possible to provide an external
bypass (through a fixed pin location) for the internal reference
amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through the selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, the aggregate sampling bandwidth is equal to
1 Msps whether it is for a single channel or distributed over
several channels). The sequencer switching is effected through
a state machine or through firmware-driven switching. A feature
provided by the sequencer is the buffering of each channel to
reduce CPU interrupt-service requirements. To accommodate
signals with varying source impedances and frequencies, it is
possible to have different sample times programmable for each
channel. Also, the signal range specification through a pair of
range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value
exceeds the programmed range; this allows fast detection of
out-of-range values without having to wait for a sequencer scan
to be completed and the CPU to read the values and check for
out-of-range values in software.
The SAR is able to digitize the output of the on-chip temperature
sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock (up to 18 MHz). The
SAR operating range is 1.71 to 5.5 V.
Figure 4. SAR ADC System Diagram
Opamps (CTBm Block)
PSoC 42X8_BLE has four opamps with Comparator modes,
which allow most common analog functions to be performed
on-chip, eliminating external components. PGAs, voltage
buffers, filters, transimpedance amplifiers, and other functions
can be realized with external passives saving power, cost, and
space. The on-chip opamps are designed with enough
bandwidth to drive the sample-and-hold circuit of the ADC
without requiring external buffering.
Temperature Sensor
PSoC 4XX8 BLE 4.2 has an on-chip temperature sensor. This
consists of a diode, which is biased by a current source that can
be disabled to save power. The temperature sensor is connected
to the ADC, which digitizes the reading and produces a temper-
ature value by using a Cypress-supplied software that includes
calibration and linearization.
Low-Power Comparators
PSoC 4XX8 BLE 4.2 has a pair of low-power comparators, which
can also operate in Deep Sleep and Hibernate modes. This
allows the analog system blocks to be disabled while retaining
the ability to monitor external voltage levels during low-power
modes. The comparator outputs are normally synchronized to
avoid metastability unless operating in an asynchronous power
mode (Hibernate) where the system wake-up circuit is activated
by a comparator-switch event.
Data and
Status Flags
Reference
Selection
External
Reference
and
Bypass
(optional )
POS
NEG
SAR Sequencer
SARADC
Inputs from other Ports
VDD/2
VDDD
VREF
AHB System Bus and Programmable Logic
Interconnect
Sequencing
and Control


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