 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CY8C4128FNI-BL493 Datasheet(PDF) 6 Page - Cypress Semiconductor |
|
||||||||||||||||||||||||||||||
CY8C4128FNI-BL493 Datasheet(HTML) 6 Page - Cypress Semiconductor |
|
|
6 / 48 page  PRELIMINARY PSoC® 4: PSoC 4XX8_BLE Family Datasheet Document Number: 001-94624 Rev. *L Page 6 of 48 Figure 3. PSoC 4XX8_BLE MCU Clocking Architecture The HFCLK signal can be divided down (see Figure 3) to generate synchronous clocks for the UDBs, and the analog and digital peripherals. There are a total of 12 clock dividers for PSoC 4XX8_BLE: ten with 16-bit divide capability and two with 16.5-bit divide capability. This allows the generation of 16 divided clock signals, which can be used by peripheral blocks. The analog clock leads the digital clocks to allow analog events to occur before the digital clock-related noise is generated. The 16-bit and 16.5-bit dividers allow a lot of flexibility in generating fine-grained frequency values and are fully supported in PSoC Creator. Reset PSoC 4XX8_BLE device can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through resets and allows the software to determine the cause of the reset. An XRES pin is reserved for an external reset to avoid complications with the configuration and multiple pin functions during power-on or reconfiguration. The XRES pin has an internal pull-up resistor that is always enabled. Voltage Reference The PSoC 4XX8_BLE reference system generates all internally required references. A one-percent voltage reference spec is provided for the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a GPIO pin or use an external reference for the SAR. Refer to Table 19, “SAR ADC AC Specifications,” on page 26 for details. BLE Radio and Subsystem PSoC 4XX8_BLE incorporates a Bluetooth Smart subsystem that contains the Physical Layer (PHY) and Link Layer (LL) engines with an embedded AES-128 security engine. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 1 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth Smart Bluetooth Specification 4.2. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine). The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna. The Bluetooth Smart Radio and Subsystem (BLESS) requires a 1.9-V minimum supply (the range varies from 1.9 V to 5.5 V). Key features of BLESS are as follows: ■ Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols ■ API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP ■ L2CAP connection-oriented channel (Bluetooth 4.1 feature) ■ GAP features ❐ Broadcaster, Observer, Peripheral, and Central roles ❐ Security mode 1: Level 1, 2, 3, and 4 ❐ Security mode 2: Level 1 and 2 ❐ User-defined advertising data ❐ Multiple bond support ■ GATT features ❐ GATT client and server ❐ Supports GATT sub-procedures ❐ 32-bit universally unique identifier (UUID) (Bluetooth 4.1 feature) ■ Security Manager (SM) ❐ Pairing methods: Just works, Passkey Entry, Out of Band, and Numeric Comparison ❐ Authenticated man-in-the-middle (MITM) protection and data signing ■ Link Layer (LL) ❐ Master and Slave roles ❐ 128-bit AES engine ❐ Encryption ❐ Low-duty cycle advertising (Bluetooth 4.1 feature) ❐ LE Ping (Bluetooth 4.1 feature) ❐ LE Data Packet Length Extension ❐ Link Layer Privacy (with extended scanning filter policy) ❐ LE Secure Connections ■ Supports all SIG-adopted BLE profiles IMO ILO EXTCLK LFCLK Prescaler SYSCLK Divider 0 (/16) PER 0_CLK Divider 9 (/16) Fractional Divider 0 (/16.5) Fractional Divider 1 (/16.5) ECO WCO HFCLK PER15_CLK Divider /2n (n=0..3) |
Similar Part No. - CY8C4128FNI-BL493 |
|
Similar Description - CY8C4128FNI-BL493 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
