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CY8C4128LQI-BL493 Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY8C4128LQI-BL493 Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 48 page PRELIMINARY PSoC® 4: PSoC 4XX8_BLE Family Datasheet Document Number: 001-94624 Rev. *L Page 4 of 48 Figure 2. Block Diagram The PSoC 4XX8_BLE devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The ARM SWD interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debugging. The PSoC Creator IDE provides fully integrated programming and debugging support for the PSoC 4XX8_BLE devices. The SWD interface is fully compatible with industry-standard third-party tools. With the ability to disable debug features, very robust flash protection, and allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC 4XX8_BLE family provides a level of security not possible with multi-chip application solutions or with microcon- trollers. Debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Because all programming, debug, and test inter- faces are disabled when maximum device security is enabled, PSoC 4XX8_BLE with device security enabled may not be returned for failure analysis. This is a trade-off the PSoC 4XX8_BLE allows the customer to make. Peripherals CPU Subsystem System Interconnect (Multi Layer AHB) PSoC 4A-BLE DeepSleep Hibernate Active/Sleep Power Modes Digital DFT Test Analog DFT System Resources Power Clock Reset Clock Control IMO Sleep Control REF POR Reset Control WIC XRES WDT ILO I/O Subsystem Peripheral Interconnect (MMIO) PCLK SWD/TC NVIC, IRQMUX Cortex M0 48 MHz FAST MUL FLASH 256/128 KB Read Accelerator SRAM 32/16 KB SRAM Controller ROM 8 KB ROM Controller NVLatches PWRSYS BOD 32-bit AHB-Lite LVD x4 UDB ... Programmable Digital UDB Port Interface & Digital System Interconnect (DSI) 36x GPIOs, 2x GPIO_OVT SAR ADC (12-bit) x1 CTBm x2 2x OpAmp Programmable Analog SARMUX High Speed I/O Matrix Bluetooth Low Energy Subsystem BLE Baseband Peripheral GFSK Modem 2.4 GHz GFSK Radio I/O: Antenna/Power/Crystal 1KB SRAM |
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