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CY8C4128FNI-BL563 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY8C4128FNI-BL563 Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 47 page  PRELIMINARY PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 5 of 47 Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in PSoC 4XX8 BLE 4.2 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher-performance processors such as Cortex-M3 and M4. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and a wakeup interrupt controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to the main processor to be switched off when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a nonmaskable interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes an SWD interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC 4XX8 BLE 4.2 has four break-point (address) comparators and two watchpoint (data) comparators. Flash The PSoC 4XX8 BLE 4.2 device has a flash module with either 128 KB or 256 KB of flash memory, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. Maximum erase and program time is 20 ms per row (256 bytes). This also applies to the emulated EEPROM. SRAM SRAM memory is retained during Hibernate. SROM The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are accessed through supervisory calls (SVC) and enable in-system programming of the flash memory. DMA A DMA engine, with eight channels, is provided that can do 32-bit transfers and has chainable ping-pong descriptors. System Resources Power System The power system is described in detail in the section Power on page 16. It provides an assurance that the voltage levels are as required for the respective modes, and can either delay the mode entry (on power-on reset (POR), for example) until voltage levels are as required or generate resets (brownout detect (BOD)) or interrupts when the power supply reaches a particular program- mable level between 1.8 and 4.5 V (low voltage detect (LVD)). PSoC 4XX8 BLE 4.2 operates with a single external supply (1.71 to 5.5 V without radio, and 1.9 V to 5.5 V with radio). The device has five different power modes; transitions between these modes are managed by the power system. PSoC 4XX8 BLE 4.2 provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. Refer to the Technical Reference Manual for more details. Clock System The PSoC 4XX8 BLE 4.2 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur. The clock system for PSoC 4XX8 BLE 4.2 consists of the internal main oscillator (IMO), the internal low-speed oscillator (ILO), the 24-MHz external crystal oscillator (ECO) and the 32-kHz watch crystal oscillator (WCO). In addition, an external clock may be supplied from a pin. IMO Clock Source The IMO is the primary source of internal clocking in PSoC 4XX8 BLE 4.2. It is trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. The IMO tolerance with Cypress-provided calibration settings is ±2%. ILO Clock Source The ILO is a very low-power oscillator, which is primarily used to generate clocks for the peripheral operation in the Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. External Crystal Oscillator (ECO) The ECO is used as the active clock for the BLE subsystem to meet the ±50-ppm clock accuracy of the Bluetooth 4.2 Specification. PSoC 4XX8 BLE 4.2 includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency. The high-accuracy ECO clock can also be used as a system clock. Watch Crystal Oscillator (WCO) The WCO is used as the sleep clock for the BLE subsystem to meet the ±500-ppm clock accuracy for the Bluetooth 4.2 Specification. The sleep clock provides an accurate sleep timing and enables wakeup at the specified advertisement and connection intervals. The WCO output can be used to realize the real-time clock (RTC) function in firmware. Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO or from the WCO; this allows the watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. With the WCO and firmware, an accurate real-time clock (within the bounds of the 32-kHz crystal accuracy) can be realized. |
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