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CYW43570 Datasheet(PDF) 14 Page - Cypress Semiconductor |
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CYW43570 Datasheet(HTML) 14 Page - Cypress Semiconductor |
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14 / 93 page  Document Number: 002-15054 Rev. *I Page 14 of 94 ADVANCE CYW43570 3.2 External Frequency Reference Table 4. Crystal Oscillator and External Clock—Requirements and Performance Parameter Conditions/Notes Crystala a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT. External Frequency Referenceb c b. See 3.2 External Frequency Reference for alternative connection methods. c. For a clock reference other than 40 MHz, 20 × log10(f/40) dB should be added to the limits, where f = the reference clock frequency in MHz. Min Typ Max Min Typ Max Units Frequency 2.4G and 5G bands: IEEE 802.11ac operation –40 –––– MHz Frequency tolerance over the lifetime of the equipment, including temperatured d. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. Without trimming –20 – 20 –20 – 20 ppm Crystal load capacitance – – 12 –––– pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – –––– μW Input impedance (WRF_XTAL_IN) Resistive – – – 30 100 – kΩ Capacitive – – 7.5 – – 7.5 pF WRF_XTAL_IN Input low level DC-coupled digital signal – – –0–0.2 V WRF_XTAL_IN Input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_IN input voltage AC-coupled analog signal – – – 400 – 1200 mVp-p Duty cycle 40 MHz clock – – – 40 50 60 % Phase Noisee (IEEE 802.11b/g) e.Assumes that the external clock has a flat phase noise response above 100 kHz. 40 MHz clock at 10 kHz offset –– ––––129 dBc/ Hz 40 MHz clock at 100 kHz offset –– ––––136 dBc/ Hz Phase Noisee (IEEE 802.11a) 40 MHz clock at 10 kHz offset –– ––––137 dBc/ Hz 40 MHz clock at 100 kHz offset –– ––––144 dBc/ Hz Phase Noisee (IEEE 802.11n, 2.4 GHz) 40 MHz clock at 10 kHz offset –– ––––134 dBc/ Hz 40 MHz clock at 100 kHz offset –– ––––141 dBc/ Hz Phase Noisee (IEEE 802.11n, 5 GHz) 40 MHz clock at 10 kHz offset –– ––––142 dBc/ Hz 40 MHz clock at 100 kHz offset –– ––––149 dBc/ Hz Phase Noisee (IEEE 802.11ac, 5 GHz) 40 MHz clock at 10 kHz offset –– ––––150 dBc/ Hz 40 MHz clock at 100 kHz offset –– ––––157 dBc/ Hz |
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