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CYW43570 Datasheet(PDF) 44 Page - Cypress Semiconductor

Part # CYW43570
Description  Single-Chip 5G WiFi IEEE 802.11ac 2횞2MAC/Baseband/Radio with IntegratedBluetooth 4.1 and EDR
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYW43570 Datasheet(HTML) 44 Page - Cypress Semiconductor

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Document Number: 002-15054 Rev. *I
Page 44 of 94
ADVANCE
CYW43570
10.2 IEEE 802.11ac Draft PHY
The CYW43570 WLAN Digital PHY is designed to comply with IEEE 802.11ac Draft and IEEE 802.11a/b/g/n dual-stream specifica-
tions to provide wireless LAN connectivity supporting data rates from 1 Mbps to 866.7 Mbps for low-power, high-performance handheld
applications.
The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates
optimized implementations of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve
maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking,
channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has
been tuned to provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence.
The key PHY features include:
Programmable data rates from MCS0–15 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in IEEE 802.11ac Draft
Supports Optional Short GI and Green Field modes in Tx and Rx
Tx and Rx LDPC for improved range and power efficiency
Beamforming support
All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive
direction.
Supports IEEE 802.11h/k for worldwide operation
Advanced algorithms for low power, enhanced sensitivity, range, and reliability
Algorithms to improve performance in presence of Bluetooth
Closed loop transmit power control
Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities
On-the-fly channel frequency and transmit power selection
Supports per packet Rx antenna diversity
Available per-packet channel quality and signal strength measurements
Designed to meet FCC and other worldwide regulatory requirements
Figure 21. WLAN PHY Block Diagram
Filters and Radio 
Comp
Frequency and 
Timing Synch
Carrier Sense, AGC, and 
Rx FSM
Radio Control Block
Common Logic Block
Filters and Radio Comp
AFE and 
Radio
MAC 
Interface
Buffers
OFDM Demodulate
Viterbi Decoder
Tx FSM
PA Comp
Modulation and 
Coding
Modulate/Spread
Frame and 
Scramble
FFT/IFFT
CCK/DSSS Demodulate
Descramble and 
Deframe
COEX


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