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CYW43570 Datasheet(PDF) 33 Page - Cypress Semiconductor |
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CYW43570 Datasheet(HTML) 33 Page - Cypress Semiconductor |
33 / 93 page Document Number: 002-15054 Rev. *I Page 33 of 94 ADVANCE CYW43570 Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW43570 UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%. Figure 16. UART Timing Table 14. Example of Common Baud Rates Desired Rate Actual Rate Error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00 Table 15. UART Timing Specifications Reference Characteristics Minimum Typical Maximum Unit 1 Delay time, BT_UART_CTS_L low to BT_UART_TXD valid – – 1.5 Bit periods 2 Setup time, BT_UART_CTS_L high before midpoint of stop bit – – 0.5 Bit periods 3 Delay time, midpoint of stop bit to BT_UART_RTS_L high – – 0.5 Bit periods BT_UART_CTS_L BT_UART_RXD 1 2 Midpoint of STOP bit BT_UART_TXD Midpoint of STOP bit 3 BT_UART_RTS_L |
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