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CYW43353 Datasheet(PDF) 36 Page - Cypress Semiconductor |
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CYW43353 Datasheet(HTML) 36 Page - Cypress Semiconductor |
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36 / 113 page  Document No. 002-14949 Rev. *F Page 36 of 113 PRELIMINARY CYW43353 7.3 I2S Interface The CYW43353 supports two independent I2S digital audio ports. The I2S signals are: ❐ I2S clock: I2S SCK ❐ I2S Word Select: I2S WS ❐ I2S Data Out: I2S SDO ❐ I2S Data In: I2S SDI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW43353 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. The clock rate in master mode is either of the following: 48 kHz x 32 bits per frame = 1.536 MHz 48 kHz x 50 bits per frame = 2.400 MHz The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. 7.3.1 I2S Timing Note: Timing values specified in Table 11 are relative to high and low threshold levels. Table 11. Timing for I2S Transmitters and Receivers Transmitter Receiver Notes Lower LImit Upper Limit Lower Limit Upper Limit Min. Max. Min. Max. Min. Max. Min. Max. Clock Period T Ttr ––– Tr –– – 1 Master Mode: Clock generated by transmitter or receiver HIGH tHC 0.35Ttr – – – 0.35Ttr –– – 2 LOWtLC 0.35Ttr – – – 0.35Ttr –– – 2 Slave Mode: Clock accepted by transmitter or receiver HIGH tHC – 0.35Ttr – – – 0.35Ttr –– 3 LOW tLC – 0.35Ttr – – – 0.35Ttr –– 3 Rise time tRC – – 0.15Ttr –– – – 4 Transmitter Delay tdtr – – – 0.8T ––– – 5 Hold time thtr 0 ––– ––– – 4 Receiver Setup time tsr – ––– – 0.2Tr –– 6 Hold time thr – ––– –0– – 6 |
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