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FAN53526UC106X Datasheet(PDF) 4 Page - ON Semiconductor

Part # FAN53526UC106X
Description  3.0 A, 2.4 MHz, Digitally Programmable TinyBuck Regulator
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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FAN53526
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4
ABSOLUTE MAXIMUM RATINGS
Stresses exceeding the absolute maximum ratings may
damage the device. The device may not function or be
operable above the recommended operating conditions and
stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the
recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings
only.
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Parameter
Min
Max
Unit
VIN
Voltage on SW, VIN Pins
IC Not Switching
−0.3
7.0
V
IC Switching
−0.3
6.5
Voltage on EN Pin
−0.3
VIN
(Note 3)
Voltage on All Other Pins
IC Not Switching
−0.3
VIN
(Note 3)
VOUT
Voltage on VOUT Pin
−0.3
6.5
V
VINOV_SLEW Maximum Slew Rate of VIN > 6.5V, PWM Switching
100
V/ms
ESD
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
2000
V
Charged Device Model per JESD22−C101
1000
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
TL
Lead Soldering Temperature, 10 Seconds
+260
°C
3. Lesser of 7V or VIN + 0.3 V.
RECOMMENDED OPERATING CONDITIONS
The Recommended Operating Conditions table defines
the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal
performance to the datasheet specifications. On
Semiconductor does not recommend exceeding them or
designing to Absolute Maximum Ratings.
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
VIN
Supply Voltage Range
2.5
5.5
V
IOUT
Output Current
0
3.0
A
TA
Operating Ambient Temperature
−40
+85
°C
TJ
Operating Junction Temperature
−40
+125
°C
Table 7. THERMAL PROPERTIES
Symbol
Parameter
Min.
Typ.
Max.
Unit
θJA
Junction−to−Ambient Thermal Resistance
(Note 4)
42
°C/W
4. Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p boards with
vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction temperature


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