FAN53555

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4

Table 5. RECOMMENDED INDUCTORS FOR LOWER−CURRENT APPLICATIONS WITH FAN53555−08−09−24

Manufacturer

Part#

L (nH)

DCR (mW Typ.)

(Note 6)

Component Dimensions

L

W

H

Toko

DFE201612R-H−R33N

330

25

3.2

2.0

1.6

1.2

Toko

DFE201612C−R47N

470

40

3.2

2.0

1.6

1.2

Cyntek

PIFE20161B−R47MS−39

470

30

3.1

2.0

1.6

1.2

SEMCO

CIGT201610HMR47SCE

470

30

3.1

2.0

1.6

0.9

LAYOUT

EN

SCL

VOUT

VIN

SW

VSEL*

GND

C1

A1

A2

C3

B3

A3

C2

D1

D3

D2

B2

C4

B4

A4

D4

E1

E3

E2

E4

AGND

SDA

A1 = VSEL for 00, 01, 04, 05, 08, 09, 13, 18, 23, 24

A1 = PGOOD for 03 79

,

C1

B1

A1

C3

B3

A3

A2

C2

D1

D3

D2

B2

C4

B4

A4

D4

E1

E3

E2

E4

B1

Figure 2. Reduced−Footprint Layout

Figure 3. Top View

PIN CONFIGURATION

Table 6. PIN DEFINITIONS

Pin #

Name

Description

A1

VSEL

(Except −03

Option)

set by the VSEL1 register.

PGOOD

(03)

Power Good. This open−drain pin pulls LOW if an overload condition occurs or soft−start is in progress.

A2

EN

Enable. The device is in Shutdown Mode when this pin is LOW. All register values are kept during shut-

down. Options 00, 01, 03, 05, 08 09, 13, 18, and 23 do not reset register values when EN is raised. The 04,

24, 79, and 042 options reset all registers to default values when EN pin is LOW. If pulled up to a low−im-

pedance voltage source greater than 1.8 V, use at least 100 W series resistor.

A3

SCL

A4

VOUT

VOUT. Sense pin for VOUT. Connect to COUT.

B1

SDA

B2, B3,

C1 – C4

GND

to these pins.

B4

AGND

Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin.